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A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文

编号：

f6a06bc7-3828-476e-ae81-e9dc50c40014
作者：

Chen, Shuai^[1] Li, Hao^[2] Chiang, Patrick Yin^[2,3]
语种：

English
期刊：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS ISSN：1063-8210 2016 年 24 卷 2 期 (578 - 586) ; FEB
收录：
关键词：

All-digital clock and data recovery (ADCDR) delay-locked loop (DLL) forwarded-clock (FC) receiver high-density interconnect jitter tolerance multicore processor process variation voltage and temperature drift
摘要：

This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today's CMOS process scaling, enables the receiver to achieve low power and area consumption. The ADCDR can enter into open loop after lock-in to save power and avoid clock dithering phenomenon. Moreover, to compensate the open loop, a phase tracking procedure is proposed to enable the ADCDR to track the phase drift due to the voltage and temperature variations. Furthermore, the all-digital delay-locked loop circuit integrated in the ADCDR can generate accurate multiphase clocks with the proposed calibrated locking algorithm in the presence of process variations. The precise multiphase clocks are essential for the half-rate sampling and Alexander-type phase detecting. Measurement results show that the receiver can operate at a data rate of 6.4 Gbits/s with a bit error rate <10(-12), consuming 7.5-mW per lane (1.2 pJ/bit) under a 0.85 V power supply. With ADCDR's phase tracking, the receiver performs better in jitter tolerance and achieves a 500-kHz bandwidth, which is high enough to track the phase drift. The receiver core occupies an area of 0.02 mm(2) per lane.
推荐引用方式
GB/T 7714：

Chen Shuai,Li Hao,Chiang Patrick Yin, et al. A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects [J].IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2016,24(2):578-586.
APA：

Chen Shuai,Li Hao,Chiang Patrick Yin.(2016).A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects .IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,24(2):578-586.
MLA：

Chen Shuai, et al. "A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects" .IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24,2(2016):578-586.

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